Accessing Generic Port on a Xilinx Schematic

 It took me a while to figure out how to access the generic port map of a VHDL entity within the schematic view, so now that Ive managed it, heres a new post about it!

The schematic editor included in Xilinx's ISE isnt very user friendly, though the concept of using a schematic to "program" your FPGA or CPLD is not a bad one... especially using a schematic for the top-level structural design allows you to have a good overview of the overall program structure. But, schematics are yuppy, and yuppies must pay for their fancy user-friendly graphical tools, no? So, lets do what we can with what we've got...